IRIX64 sdsshost 6.5 6.5.6m 10181058 IP19
CPU Board at Slot 2: (Enabled)
  Processor 0 at Slot 2/Slice 0: 200 Mhz R4400 with 4 MB secondary cache (Enabled)
  Processor 1 at Slot 2/Slice 1: 200 Mhz R4400 with 4 MB secondary cache (Enabled)
  Processor 2 at Slot 2/Slice 2: 200 Mhz R4400 with 4 MB secondary cache (Enabled)
  Processor 3 at Slot 2/Slice 3: 200 Mhz R4400 with 4 MB secondary cache (Enabled)
CPU Board at Slot 3: (Enabled)
  Processor 4 at Slot 3/Slice 0: 200 Mhz R4400 with 4 MB secondary cache (Enabled)
  Processor 5 at Slot 3/Slice 1: 200 Mhz R4400 with 4 MB secondary cache (Enabled)
CPU: MIPS R4400 Processor Chip Revision: 6.0
FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0
Main memory size: 256 Mbytes, 1-way interleaved
MC3 Memory Board at Slot 1: 256 MB of memory (Enabled)
  Bank A contains 64 MB SIMMS (Enabled)
Instruction cache size: 16 Kbytes
Data cache size: 16 Kbytes
Secondary unified instruction/data cache size: 4 Mbytes
Integral SCSI controller 0: Version WD33C95A, single ended, revision 0