TILE 1 VDDA: 1880 IDDA: 120.0 VDDD: 1664 IDDD: 525.0 TILE 2 VDDA: 1876 IDDA: 320.0 VDDD: 1668 IDDD: 535.0 TILE 3 VDDA: 1876 IDDA: 140.0 VDDD: 1672 IDDD: 505.0 TILE 4 VDDA: 1876 IDDA: 145.0 VDDD: 1664 IDDD: 515.0 TILE 5 VDDA: 1868 IDDA: 100.0 VDDD: 1656 IDDD: 430.0 TILE 6 VDDA: 1864 IDDA: 95.0 VDDD: 1668 IDDD: 695.0 TILE 7 VDDA: 1864 IDDA: 110.0 VDDD: 1668 IDDD: 445.0 TILE 8 VDDA: 1880 IDDA: 105.0 VDDD: 1656 IDDD: 440.0 verified root chip 11 verified root chip 41 verified root chip 71 unable to verify root chip 101 good root chips: [11, 41, 71] [11, 41, 71] TILE 1 VDDA: 1876 IDDA: 135.0 VDDD: 1660 IDDD: 525.0 TILE 2 VDDA: 1872 IDDA: 335.0 VDDD: 1664 IDDD: 535.0 TILE 3 VDDA: 1872 IDDA: 135.0 VDDD: 1676 IDDD: 515.0 TILE 4 VDDA: 1876 IDDA: 150.0 VDDD: 1668 IDDD: 530.0 TILE 5 VDDA: 1864 IDDA: 85.0 VDDD: 1652 IDDD: 445.0 TILE 6 VDDA: 1864 IDDA: 95.0 VDDD: 1664 IDDD: 705.0 TILE 7 VDDA: 1860 IDDA: 105.0 VDDD: 1668 IDDD: 435.0 TILE 8 VDDA: 1876 IDDA: 80.0 VDDD: 1656 IDDD: 445.0 path including 100 chips 1-21-12 True 1-22-42 True 1-23-72 True 1-21-13 True 1-22-43 True 1-23-73 True 1-21-14 True 1-22-44 True 1-23-74 True 1-21-15 True 1-22-45 True 1-23-75 True 1-21-16 True 1-22-46 True 1-23-76 True 1-21-17 True 1-22-47 True 1-23-77 True 1-21-18 True 1-22-48 True 1-23-78 True 1-21-19 True 1-22-49 True 1-23-79 True 1-21-20 True 1-22-50 True 1-23-80 True 1-21-30 True 1-22-60 True 1-23-90 True 1-21-29 True 1-22-59 True 1-23-89 True 1-21-28 True 1-22-58 True 1-23-88 True 1-21-27 True 1-22-57 True 1-23-87 True 1-21-26 True 1-22-56 False 1-23-86 True 1-21-25 True 1-23-85 True 1-21-24 True 1-23-84 True 1-21-23 True 1-23-83 True 1-21-22 True 1-23-82 True 1-21-21 True 1-23-81 True 1-21-31 True 1-23-91 True 1-21-32 True 1-23-92 True 1-21-33 True 1-23-93 True 1-21-34 True 1-23-94 True 1-21-35 True 1-23-95 True 1-21-36 True 1-23-96 True 1-21-37 True 1-23-97 True 1-21-38 True 1-23-98 True 1-21-39 True 1-23-99 True 1-21-40 True 1-23-100 True 1-23-110 True 1-23-109 True 1-23-108 True 1-23-107 True 1-23-106 True 1-23-105 True 1-23-104 True 1-23-103 True 1-23-102 True 1-23-101 True TILE 1 VDDA: 1876 IDDA: 110.0 VDDD: 1664 IDDD: 520.0 TILE 2 VDDA: 1872 IDDA: 340.0 VDDD: 1672 IDDD: 520.0 TILE 3 VDDA: 1876 IDDA: 125.0 VDDD: 1672 IDDD: 515.0 TILE 4 VDDA: 1876 IDDA: 140.0 VDDD: 1664 IDDD: 510.0 TILE 5 VDDA: 1868 IDDA: 90.0 VDDD: 1656 IDDD: 435.0 TILE 6 VDDA: 1864 IDDA: 105.0 VDDD: 1664 IDDD: 680.0 TILE 7 VDDA: 1864 IDDA: 115.0 VDDD: 1664 IDDD: 450.0 TILE 8 VDDA: 1880 IDDA: 80.0 VDDD: 1656 IDDD: 440.0 path inlcuding 100 chips 1-21-12 already verified 1-22-42 already verified 1-23-72 already verified 1-21-13 already verified 1-22-43 already verified 1-23-73 already verified 1-21-14 already verified 1-22-44 already verified 1-23-74 already verified 1-21-15 already verified 1-22-45 already verified 1-23-75 already verified 1-21-16 already verified 1-22-46 already verified 1-23-76 already verified 1-21-17 already verified 1-22-47 already verified 1-23-77 already verified 1-21-18 already verified 1-22-48 already verified 1-23-78 already verified 1-21-19 already verified 1-22-49 already verified 1-23-79 already verified 1-21-20 already verified 1-22-50 already verified 1-23-80 already verified 1-21-30 already verified 1-22-60 already verified 1-23-90 already verified 1-21-40 True 1-22-70 True 1-23-100 True 1-21-39 already verified 1-22-69 True 1-23-110 already verified 1-21-38 already verified 1-22-68 True 1-23-109 already verified 1-21-37 already verified 1-22-67 True 1-23-108 already verified 1-21-36 already verified 1-22-66 True 1-23-107 already verified 1-21-35 already verified 1-22-65 True 1-23-106 already verified 1-21-34 already verified 1-22-64 True 1-23-105 already verified 1-21-33 already verified 1-22-63 True 1-23-104 already verified 1-21-32 already verified 1-22-62 True 1-23-103 already verified 1-21-31 already verified 1-22-61 True 1-23-102 already verified 1-21-21 already verified 1-22-51 True 1-23-101 already verified 1-21-22 already verified 1-22-52 True 1-23-91 True 1-21-23 already verified 1-22-53 True 1-23-92 already verified 1-21-24 already verified 1-22-54 True 1-23-93 already verified 1-21-25 already verified 1-22-55 True 1-23-94 already verified 1-21-26 already verified 1-22-56 True 1-23-95 already verified 1-21-27 already verified 1-22-57 False 1-23-96 already verified 1-21-28 already verified 1-23-97 already verified 1-21-29 already verified 1-23-98 already verified 1-23-99 already verified 1-23-89 True 1-23-88 already verified 1-23-87 already verified 1-23-86 already verified 1-23-85 already verified 1-23-84 already verified 1-23-83 already verified 1-23-82 already verified 1-23-81 already verified TILE 1 VDDA: 1880 IDDA: 125.0 VDDD: 1668 IDDD: 530.0 TILE 2 VDDA: 1872 IDDA: 330.0 VDDD: 1672 IDDD: 540.0 TILE 3 VDDA: 1876 IDDA: 135.0 VDDD: 1672 IDDD: 525.0 TILE 4 VDDA: 1876 IDDA: 155.0 VDDD: 1668 IDDD: 530.0 TILE 5 VDDA: 1868 IDDA: 95.0 VDDD: 1656 IDDD: 470.0 TILE 6 VDDA: 1864 IDDA: 85.0 VDDD: 1664 IDDD: 685.0 TILE 7 VDDA: 1864 IDDA: 105.0 VDDD: 1664 IDDD: 445.0 TILE 8 VDDA: 1876 IDDA: 85.0 VDDD: 1660 IDDD: 440.0 path inlcuding 100 chips 1-21-21 True 1-22-51 True 1-23-81 True 1-21-31 already verified 1-22-61 already verified 1-23-91 already verified 1-21-32 already verified 1-22-62 already verified 1-23-101 already verified 1-21-42 True 1-22-72 True 1-23-102 already verified 1-21-52 True 1-22-82 True 1-23-92 True 1-21-53 already verified 1-22-83 already verified 1-23-93 already verified 1-21-63 True 1-22-73 True 1-23-103 True 1-21-64 already verified 1-22-74 already verified 1-23-104 already verified 1-21-54 True 1-22-84 True 1-23-94 True 1-21-44 True 1-22-85 already verified 1-23-95 already verified 1-21-43 already verified 1-22-75 True 1-23-105 True 1-21-33 True 1-22-65 True 1-23-106 already verified 1-21-23 True 1-22-55 True 1-23-96 True 1-21-22 already verified 1-22-45 True 1-23-86 True 1-21-12 True 1-22-35 True 1-23-76 True 1-21-13 already verified 1-22-34 already verified 1-23-66 True 1-21-14 already verified 1-22-24 True 1-23-56 True 1-21-15 already verified 1-22-25 already verified 1-23-46 True 1-21-16 already verified 1-22-26 already verified 1-23-36 True 1-21-17 already verified 1-22-27 already verified 1-23-37 already verified 1-21-18 already verified 1-22-28 already verified 1-23-47 True 1-21-19 already verified 1-22-38 True 1-23-57 True 1-21-29 True 1-22-48 True 1-23-67 True 1-21-39 True 1-22-58 True 1-23-77 True 1-21-49 True 1-22-68 True 1-23-87 True 1-21-59 True 1-22-78 True 1-23-97 True 1-21-69 True 1-22-88 True 1-23-107 True 1-21-79 True 1-22-98 True 1-23-108 already verified 1-21-89 True 1-22-99 already verified 1-23-109 already verified 1-21-90 already verified 1-22-100 already verified 1-23-110 already verified 1-21-80 already verified 1-21-70 True 1-21-60 already verified 1-21-50 already verified 1-21-40 True 1-21-30 already verified 1-21-20 already verified *************************************** ***Starting Test of Individual Chips*** *************************************** starting test of 31 to 41 successfully tested uart 31 41 starting test of 32 to 22 successfully tested uart 32 22 starting test of 52 to 62 successfully tested uart 52 62 starting test of 53 to 43 successfully tested uart 53 43 starting test of 63 to 73 successfully tested uart 63 73 starting test of 64 to 74 successfully tested uart 64 74 starting test of 44 to 34 successfully tested uart 44 34 starting test of 23 to 13 successfully tested uart 23 13 starting test of 14 to 24 successfully tested uart 14 24 starting test of 15 to 25 successfully tested uart 15 25 starting test of 16 to 26 successfully tested uart 16 26 starting test of 17 to 27 successfully tested uart 17 27 starting test of 18 to 28 successfully tested uart 18 28 starting test of 61 to 71 successfully tested uart 61 71 starting test of 82 to 92 successfully tested uart 82 92 starting test of 83 to 93 successfully tested uart 83 93 starting test of 84 to 94 successfully tested uart 84 94 starting test of 85 to 95 successfully tested uart 85 95 starting test of 35 to 25 successfully tested uart 35 25 starting test of 26 to 36 successfully tested uart 26 36 starting test of 27 to 37 successfully tested uart 27 37 starting test of 98 to 108 successfully tested uart 98 108 starting test of 99 to 109 successfully tested uart 99 109 starting test of 56 to 57 56 57 2 sided connection broken not testing, 57 56 untested [] bad (one-way) links: {(56, 57), (57, 56)} tested 360 uarts writing configuration tile-id-106-pacman-tile-6-hydra-network.json, including 100 chips 38 31 31 100