TILE 1 VDDA: 1872 IDDA: 145.0 VDDD: 1660 IDDD: 485.0 TILE 2 VDDA: 1876 IDDA: 145.0 VDDD: 1672 IDDD: 520.0 TILE 3 VDDA: 1868 IDDA: 140.0 VDDD: 1664 IDDD: 510.0 TILE 4 VDDA: 1872 IDDA: 130.0 VDDD: 1672 IDDD: 520.0 TILE 5 VDDA: 1868 IDDA: 80.0 VDDD: 1664 IDDD: 465.0 TILE 6 VDDA: 1860 IDDA: 95.0 VDDD: 1664 IDDD: 710.0 TILE 7 VDDA: 1868 IDDA: 110.0 VDDD: 1664 IDDD: 450.0 TILE 8 VDDA: 1864 IDDA: 100.0 VDDD: 1668 IDDD: 425.0 verified root chip 11 verified root chip 41 verified root chip 71 verified root chip 101 good root chips: [11, 41, 71, 101] [11, 41, 71, 101] TILE 1 VDDA: 1876 IDDA: 145.0 VDDD: 1656 IDDD: 495.0 TILE 2 VDDA: 1876 IDDA: 130.0 VDDD: 1668 IDDD: 520.0 TILE 3 VDDA: 1868 IDDA: 145.0 VDDD: 1660 IDDD: 525.0 TILE 4 VDDA: 1872 IDDA: 120.0 VDDD: 1672 IDDD: 525.0 TILE 5 VDDA: 1860 IDDA: 100.0 VDDD: 1668 IDDD: 465.0 TILE 6 VDDA: 1864 IDDA: 105.0 VDDD: 1664 IDDD: 700.0 TILE 7 VDDA: 1872 IDDA: 90.0 VDDD: 1664 IDDD: 450.0 TILE 8 VDDA: 1868 IDDA: 115.0 VDDD: 1672 IDDD: 425.0 path including 100 chips 1-5-12 True 1-6-42 True 1-7-72 True 1-8-102 True 1-5-13 True 1-6-43 True 1-7-73 True 1-8-103 True 1-5-14 True 1-6-44 True 1-7-74 True 1-8-104 True 1-5-15 True 1-6-45 True 1-7-75 True 1-8-105 True 1-5-16 True 1-6-46 True 1-7-76 True 1-8-106 True 1-5-17 True 1-6-47 True 1-7-77 True 1-8-107 True 1-5-18 True 1-6-48 True 1-7-78 True 1-8-108 True 1-5-19 True 1-6-49 True 1-7-79 True 1-8-109 True 1-5-20 True 1-6-50 True 1-7-80 True 1-8-110 True 1-5-30 True 1-6-60 True 1-7-90 True 1-8-100 True 1-5-29 True 1-6-59 True 1-7-89 True 1-8-99 True 1-5-28 True 1-6-58 True 1-7-88 True 1-8-98 True 1-5-27 True 1-6-57 True 1-7-87 True 1-8-97 True 1-5-26 True 1-6-56 True 1-7-86 True 1-8-96 True 1-5-25 True 1-6-55 True 1-7-85 True 1-8-95 True 1-5-24 True 1-6-54 True 1-7-84 True 1-8-94 True 1-5-23 True 1-6-53 True 1-7-83 True 1-8-93 True 1-5-22 True 1-6-52 False 1-7-82 True 1-8-92 True 1-5-21 True 1-7-81 True 1-8-91 True 1-5-31 True 1-5-32 True 1-5-33 True 1-5-34 True 1-5-35 True 1-5-36 True 1-5-37 True 1-5-38 True 1-5-39 True 1-5-40 True TILE 1 VDDA: 1872 IDDA: 135.0 VDDD: 1660 IDDD: 495.0 TILE 2 VDDA: 1876 IDDA: 145.0 VDDD: 1672 IDDD: 510.0 TILE 3 VDDA: 1872 IDDA: 145.0 VDDD: 1668 IDDD: 525.0 TILE 4 VDDA: 1876 IDDA: 130.0 VDDD: 1672 IDDD: 515.0 TILE 5 VDDA: 1864 IDDA: 95.0 VDDD: 1664 IDDD: 455.0 TILE 6 VDDA: 1860 IDDA: 90.0 VDDD: 1664 IDDD: 705.0 TILE 7 VDDA: 1872 IDDA: 90.0 VDDD: 1664 IDDD: 450.0 TILE 8 VDDA: 1864 IDDA: 85.0 VDDD: 1672 IDDD: 430.0 path inlcuding 100 chips 1-5-12 already verified 1-6-42 already verified 1-7-72 already verified 1-8-102 already verified 1-5-13 already verified 1-6-43 already verified 1-7-73 already verified 1-8-103 already verified 1-5-14 already verified 1-6-44 already verified 1-7-74 already verified 1-8-104 already verified 1-5-15 already verified 1-6-45 already verified 1-7-75 already verified 1-8-105 already verified 1-5-16 already verified 1-6-46 already verified 1-7-76 already verified 1-8-106 already verified 1-5-17 already verified 1-6-47 already verified 1-7-77 already verified 1-8-107 already verified 1-5-18 already verified 1-6-48 already verified 1-7-78 already verified 1-8-108 already verified 1-5-19 already verified 1-6-49 already verified 1-7-79 already verified 1-8-109 already verified 1-5-20 already verified 1-6-50 already verified 1-7-80 already verified 1-8-110 already verified 1-5-30 already verified 1-6-40 True 1-7-70 True 1-8-100 already verified 1-5-29 already verified 1-6-39 already verified 1-7-69 True 1-8-99 already verified 1-5-28 already verified 1-6-38 already verified 1-7-68 True 1-8-98 already verified 1-5-27 already verified 1-6-37 already verified 1-7-67 True 1-8-97 already verified 1-5-26 already verified 1-6-36 already verified 1-7-66 True 1-8-96 already verified 1-5-25 already verified 1-6-35 already verified 1-7-65 True 1-8-95 already verified 1-5-24 already verified 1-6-34 already verified 1-7-64 True 1-8-94 already verified 1-5-23 already verified 1-6-33 already verified 1-7-63 True 1-8-93 already verified 1-5-22 already verified 1-6-32 already verified 1-7-62 True 1-8-92 already verified 1-5-21 already verified 1-6-31 already verified 1-7-61 True 1-8-91 already verified 1-7-51 True 1-8-81 True 1-7-52 True 1-8-82 already verified 1-7-53 False 1-8-83 already verified 1-8-84 already verified 1-8-85 already verified 1-8-86 already verified 1-8-87 already verified 1-8-88 already verified 1-8-89 already verified 1-8-90 already verified TILE 1 VDDA: 1876 IDDA: 135.0 VDDD: 1656 IDDD: 500.0 TILE 2 VDDA: 1876 IDDA: 135.0 VDDD: 1668 IDDD: 510.0 TILE 3 VDDA: 1872 IDDA: 125.0 VDDD: 1664 IDDD: 525.0 TILE 4 VDDA: 1876 IDDA: 130.0 VDDD: 1672 IDDD: 515.0 TILE 5 VDDA: 1872 IDDA: 90.0 VDDD: 1664 IDDD: 460.0 TILE 6 VDDA: 1864 IDDA: 110.0 VDDD: 1668 IDDD: 670.0 TILE 7 VDDA: 1872 IDDA: 90.0 VDDD: 1664 IDDD: 450.0 TILE 8 VDDA: 1864 IDDA: 90.0 VDDD: 1672 IDDD: 435.0 path inlcuding 100 chips 1-5-12 already verified 1-6-42 already verified 1-7-72 already verified 1-8-102 already verified 1-5-13 already verified 1-6-43 already verified 1-7-73 already verified 1-8-103 already verified 1-5-14 already verified 1-6-44 already verified 1-7-74 already verified 1-8-104 already verified 1-5-15 already verified 1-6-45 already verified 1-7-75 already verified 1-8-105 already verified 1-5-16 already verified 1-6-46 already verified 1-7-76 already verified 1-8-106 already verified 1-5-17 already verified 1-6-47 already verified 1-7-77 already verified 1-8-107 already verified 1-5-18 already verified 1-6-48 already verified 1-7-78 already verified 1-8-108 already verified 1-5-19 already verified 1-6-49 already verified 1-7-79 already verified 1-8-109 already verified 1-5-20 already verified 1-6-50 already verified 1-7-80 already verified 1-8-110 already verified 1-5-30 already verified 1-6-40 already verified 1-7-70 already verified 1-8-100 already verified 1-5-29 already verified 1-6-39 already verified 1-7-60 True 1-8-90 True 1-5-28 already verified 1-6-38 already verified 1-7-59 already verified 1-8-89 already verified 1-5-27 already verified 1-6-37 already verified 1-7-69 True 1-8-99 True 1-5-26 already verified 1-6-36 already verified 1-7-68 already verified 1-8-98 already verified 1-5-25 already verified 1-6-35 already verified 1-7-58 True 1-8-88 True 1-5-24 already verified 1-6-34 already verified 1-7-57 already verified 1-8-87 already verified 1-5-23 already verified 1-6-33 already verified 1-7-67 True 1-8-97 True 1-5-22 already verified 1-6-32 already verified 1-7-66 already verified 1-8-96 already verified 1-5-21 already verified 1-6-31 already verified 1-7-56 True 1-8-86 True 1-7-55 already verified 1-8-85 already verified 1-7-65 True 1-8-95 True 1-7-64 already verified 1-8-94 already verified 1-7-54 True 1-8-84 True 1-7-53 already verified 1-8-83 already verified 1-7-63 True 1-8-93 True 1-7-62 already verified 1-8-92 already verified 1-7-52 True 1-8-82 True 1-7-51 already verified 1-8-81 already verified 1-7-61 already verified 1-8-91 already verified *************************************** ***Starting Test of Individual Chips*** *************************************** starting test of 12 to 22 successfully tested uart 12 22 starting test of 13 to 23 successfully tested uart 13 23 starting test of 14 to 24 successfully tested uart 14 24 starting test of 15 to 25 successfully tested uart 15 25 starting test of 16 to 26 successfully tested uart 16 26 starting test of 17 to 27 successfully tested uart 17 27 starting test of 18 to 28 successfully tested uart 18 28 starting test of 19 to 29 successfully tested uart 19 29 starting test of 30 to 40 successfully tested uart 30 40 starting test of 29 to 39 successfully tested uart 29 39 starting test of 28 to 38 successfully tested uart 28 38 starting test of 27 to 37 successfully tested uart 27 37 starting test of 26 to 36 successfully tested uart 26 36 starting test of 25 to 35 successfully tested uart 25 35 starting test of 24 to 34 successfully tested uart 24 34 starting test of 23 to 33 successfully tested uart 23 33 starting test of 22 to 32 successfully tested uart 22 32 not testing, 21 11 starting test of 41 to 51 successfully tested uart 41 51 starting test of 42 to 32 successfully tested uart 42 32 starting test of 42 to 52 successfully tested uart 42 52 starting test of 43 to 33 successfully tested uart 43 33 starting test of 43 to 53 successfully tested uart 43 53 starting test of 44 to 34 successfully tested uart 44 34 starting test of 44 to 54 successfully tested uart 44 54 starting test of 45 to 35 successfully tested uart 45 35 starting test of 45 to 55 successfully tested uart 45 55 starting test of 46 to 36 successfully tested uart 46 36 starting test of 46 to 56 successfully tested uart 46 56 starting test of 47 to 37 successfully tested uart 47 37 starting test of 47 to 57 successfully tested uart 47 57 starting test of 48 to 38 successfully tested uart 48 38 starting test of 48 to 58 successfully tested uart 48 58 starting test of 49 to 39 successfully tested uart 49 39 starting test of 49 to 59 successfully tested uart 49 59 not testing, 31 41 starting test of 71 to 81 successfully tested uart 71 81 starting test of 72 to 62 successfully tested uart 72 62 starting test of 72 to 82 successfully tested uart 72 82 starting test of 73 to 63 successfully tested uart 73 63 starting test of 73 to 83 successfully tested uart 73 83 starting test of 74 to 64 successfully tested uart 74 64 starting test of 74 to 84 successfully tested uart 74 84 starting test of 75 to 65 successfully tested uart 75 65 starting test of 75 to 85 successfully tested uart 75 85 starting test of 76 to 66 successfully tested uart 76 66 starting test of 76 to 86 successfully tested uart 76 86 starting test of 77 to 67 successfully tested uart 77 67 starting test of 77 to 87 successfully tested uart 77 87 starting test of 78 to 68 successfully tested uart 78 68 starting test of 78 to 88 successfully tested uart 78 88 starting test of 79 to 69 successfully tested uart 79 69 starting test of 79 to 89 successfully tested uart 79 89 starting test of 53 to 52 53 52 2 sided connection broken not testing, 52 53 not testing, 61 71 starting test of 102 to 92 successfully tested uart 102 92 starting test of 103 to 93 successfully tested uart 103 93 starting test of 104 to 94 successfully tested uart 104 94 starting test of 105 to 95 successfully tested uart 105 95 starting test of 106 to 96 successfully tested uart 106 96 starting test of 107 to 97 successfully tested uart 107 97 starting test of 108 to 98 successfully tested uart 108 98 starting test of 109 to 99 successfully tested uart 109 99 not testing, 91 101 untested [] bad (one-way) links: {(52, 53), (53, 52)} tested 352 uarts writing configuration tile-id-202-pacman-tile-2-hydra-network.json, including 100 chips 20 20 30 30 100