TILE 1 VDDA: 1876 IDDA: 115.0 VDDD: 1656 IDDD: 510.0 TILE 2 VDDA: 1876 IDDA: 135.0 VDDD: 1676 IDDD: 505.0 TILE 3 VDDA: 1868 IDDA: 150.0 VDDD: 1664 IDDD: 520.0 TILE 4 VDDA: 1876 IDDA: 125.0 VDDD: 1672 IDDD: 525.0 TILE 5 VDDA: 1860 IDDA: 110.0 VDDD: 1664 IDDD: 465.0 TILE 6 VDDA: 1864 IDDA: 90.0 VDDD: 1668 IDDD: 690.0 TILE 7 VDDA: 1868 IDDA: 95.0 VDDD: 1664 IDDD: 445.0 TILE 8 VDDA: 1864 IDDA: 80.0 VDDD: 1668 IDDD: 430.0 verified root chip 11 verified root chip 41 verified root chip 71 verified root chip 101 good root chips: [11, 41, 71, 101] [11, 41, 71, 101] TILE 1 VDDA: 1876 IDDA: 155.0 VDDD: 1656 IDDD: 510.0 TILE 2 VDDA: 1872 IDDA: 145.0 VDDD: 1672 IDDD: 510.0 TILE 3 VDDA: 1868 IDDA: 140.0 VDDD: 1664 IDDD: 520.0 TILE 4 VDDA: 1872 IDDA: 130.0 VDDD: 1672 IDDD: 525.0 TILE 5 VDDA: 1860 IDDA: 85.0 VDDD: 1664 IDDD: 455.0 TILE 6 VDDA: 1864 IDDA: 100.0 VDDD: 1668 IDDD: 690.0 TILE 7 VDDA: 1868 IDDA: 90.0 VDDD: 1664 IDDD: 450.0 TILE 8 VDDA: 1864 IDDA: 100.0 VDDD: 1672 IDDD: 445.0 path including 100 chips 1-9-12 True 1-10-42 True 1-11-72 True 1-12-102 True 1-9-13 True 1-10-43 True 1-11-73 False 1-12-103 True 1-9-14 True 1-10-44 True 1-12-104 True 1-9-15 True 1-10-45 True 1-12-105 True 1-9-16 True 1-10-46 True 1-12-106 True 1-9-17 True 1-10-47 True 1-12-107 True 1-9-18 True 1-10-48 True 1-12-108 True 1-9-19 True 1-10-49 True 1-12-109 True 1-9-20 True 1-10-50 True 1-12-110 True 1-9-30 True 1-10-60 True 1-12-100 True 1-9-29 True 1-10-59 True 1-12-99 True 1-9-28 True 1-10-58 True 1-12-98 True 1-9-27 True 1-10-57 True 1-12-97 True 1-9-26 True 1-10-56 True 1-12-96 True 1-9-25 True 1-10-55 True 1-12-95 True 1-9-24 True 1-10-54 True 1-12-94 True 1-9-23 True 1-10-53 True 1-12-93 True 1-9-22 True 1-10-52 True 1-12-92 True 1-9-21 True 1-10-51 True 1-12-91 True 1-9-31 True 1-10-61 True 1-9-32 True 1-10-62 True 1-9-33 True 1-10-63 True 1-9-34 True 1-10-64 True 1-9-35 True 1-10-65 True 1-9-36 True 1-10-66 True 1-9-37 True 1-10-67 True 1-9-38 True 1-10-68 True 1-9-39 True 1-10-69 True 1-9-40 True 1-10-70 True TILE 1 VDDA: 1876 IDDA: 135.0 VDDD: 1660 IDDD: 525.0 TILE 2 VDDA: 1876 IDDA: 130.0 VDDD: 1672 IDDD: 515.0 TILE 3 VDDA: 1868 IDDA: 130.0 VDDD: 1668 IDDD: 515.0 TILE 4 VDDA: 1872 IDDA: 120.0 VDDD: 1672 IDDD: 525.0 TILE 5 VDDA: 1856 IDDA: 110.0 VDDD: 1660 IDDD: 455.0 TILE 6 VDDA: 1864 IDDA: 90.0 VDDD: 1664 IDDD: 695.0 TILE 7 VDDA: 1868 IDDA: 95.0 VDDD: 1664 IDDD: 450.0 TILE 8 VDDA: 1864 IDDA: 100.0 VDDD: 1672 IDDD: 425.0 path inlcuding 100 chips 1-9-12 already verified 1-10-42 already verified 1-11-72 already verified 1-12-102 already verified 1-9-13 already verified 1-10-43 already verified 1-11-82 True 1-12-103 already verified 1-9-14 already verified 1-10-44 already verified 1-11-83 True 1-12-104 already verified 1-9-15 already verified 1-10-45 already verified 1-11-73 True 1-12-105 already verified 1-9-16 already verified 1-10-46 already verified 1-11-74 True 1-12-106 already verified 1-9-17 already verified 1-10-47 already verified 1-11-75 True 1-12-107 already verified 1-9-18 already verified 1-10-48 already verified 1-11-76 True 1-12-108 already verified 1-9-19 already verified 1-10-49 already verified 1-11-77 True 1-12-109 already verified 1-9-20 already verified 1-10-50 already verified 1-11-78 True 1-12-110 already verified 1-9-30 already verified 1-10-60 already verified 1-11-79 True 1-12-100 already verified 1-9-29 already verified 1-10-59 already verified 1-11-80 True 1-12-99 already verified 1-9-28 already verified 1-10-58 already verified 1-11-90 True 1-12-98 already verified 1-9-27 already verified 1-10-57 already verified 1-11-89 True 1-12-97 already verified 1-9-26 already verified 1-10-56 already verified 1-11-88 True 1-12-96 already verified 1-9-25 already verified 1-10-55 already verified 1-11-87 True 1-12-95 already verified 1-9-24 already verified 1-10-54 already verified 1-11-86 True 1-12-94 already verified 1-9-23 already verified 1-10-53 already verified 1-11-85 True 1-12-93 already verified 1-9-22 already verified 1-10-52 already verified 1-11-84 True 1-12-92 already verified 1-9-21 already verified 1-10-51 already verified 1-12-91 already verified 1-9-31 already verified 1-10-61 already verified 1-12-81 True 1-9-32 already verified 1-10-62 already verified 1-9-33 already verified 1-10-63 already verified 1-9-34 already verified 1-10-64 already verified 1-9-35 already verified 1-10-65 already verified 1-9-36 already verified 1-10-66 already verified 1-9-37 already verified 1-10-67 already verified 1-9-38 already verified 1-10-68 already verified 1-9-39 already verified 1-10-69 already verified 1-9-40 already verified 1-10-70 already verified *************************************** ***Starting Test of Individual Chips*** *************************************** starting test of 11 to 21 successfully tested uart 11 21 starting test of 12 to 22 successfully tested uart 12 22 starting test of 13 to 23 successfully tested uart 13 23 starting test of 14 to 24 successfully tested uart 14 24 starting test of 15 to 25 successfully tested uart 15 25 starting test of 16 to 26 successfully tested uart 16 26 starting test of 17 to 27 successfully tested uart 17 27 starting test of 18 to 28 successfully tested uart 18 28 starting test of 19 to 29 successfully tested uart 19 29 starting test of 30 to 40 successfully tested uart 30 40 starting test of 29 to 39 successfully tested uart 29 39 starting test of 28 to 38 successfully tested uart 28 38 starting test of 27 to 37 successfully tested uart 27 37 starting test of 26 to 36 successfully tested uart 26 36 starting test of 25 to 35 successfully tested uart 25 35 starting test of 24 to 34 successfully tested uart 24 34 starting test of 23 to 33 successfully tested uart 23 33 starting test of 22 to 32 successfully tested uart 22 32 starting test of 31 to 41 successfully tested uart 31 41 starting test of 32 to 42 successfully tested uart 32 42 starting test of 33 to 43 successfully tested uart 33 43 starting test of 34 to 44 successfully tested uart 34 44 starting test of 35 to 45 successfully tested uart 35 45 starting test of 36 to 46 successfully tested uart 36 46 starting test of 37 to 47 successfully tested uart 37 47 starting test of 38 to 48 successfully tested uart 38 48 starting test of 39 to 49 successfully tested uart 39 49 starting test of 40 to 50 successfully tested uart 40 50 starting test of 41 to 51 successfully tested uart 41 51 starting test of 42 to 52 successfully tested uart 42 52 starting test of 43 to 53 successfully tested uart 43 53 starting test of 44 to 54 successfully tested uart 44 54 starting test of 45 to 55 successfully tested uart 45 55 starting test of 46 to 56 successfully tested uart 46 56 starting test of 47 to 57 successfully tested uart 47 57 starting test of 48 to 58 successfully tested uart 48 58 starting test of 49 to 59 successfully tested uart 49 59 starting test of 60 to 70 successfully tested uart 60 70 starting test of 59 to 69 successfully tested uart 59 69 starting test of 58 to 68 successfully tested uart 58 68 starting test of 57 to 67 successfully tested uart 57 67 starting test of 56 to 66 successfully tested uart 56 66 starting test of 55 to 65 successfully tested uart 55 65 starting test of 54 to 64 successfully tested uart 54 64 starting test of 53 to 63 successfully tested uart 53 63 starting test of 52 to 62 successfully tested uart 52 62 starting test of 61 to 71 successfully tested uart 61 71 starting test of 62 to 72 successfully tested uart 62 72 starting test of 63 to 73 successfully tested uart 63 73 starting test of 64 to 74 successfully tested uart 64 74 starting test of 65 to 75 successfully tested uart 65 75 starting test of 66 to 76 successfully tested uart 66 76 starting test of 67 to 77 successfully tested uart 67 77 starting test of 68 to 78 successfully tested uart 68 78 starting test of 69 to 79 successfully tested uart 69 79 starting test of 70 to 80 successfully tested uart 70 80 starting test of 71 to 81 successfully tested uart 71 81 starting test of 72 to 73 72 73 2 sided connection broken starting test of 82 to 81 successfully tested uart 82 81 starting test of 82 to 92 successfully tested uart 82 92 starting test of 83 to 84 successfully tested uart 83 84 starting test of 83 to 93 successfully tested uart 83 93 not testing, 73 72 starting test of 74 to 84 successfully tested uart 74 84 starting test of 75 to 85 successfully tested uart 75 85 starting test of 76 to 86 successfully tested uart 76 86 starting test of 77 to 87 successfully tested uart 77 87 starting test of 78 to 88 successfully tested uart 78 88 starting test of 79 to 89 successfully tested uart 79 89 starting test of 90 to 100 successfully tested uart 90 100 starting test of 89 to 99 successfully tested uart 89 99 starting test of 88 to 98 successfully tested uart 88 98 starting test of 87 to 97 successfully tested uart 87 97 starting test of 86 to 96 successfully tested uart 86 96 starting test of 85 to 95 successfully tested uart 85 95 starting test of 84 to 94 successfully tested uart 84 94 starting test of 101 to 91 successfully tested uart 101 91 starting test of 102 to 92 successfully tested uart 102 92 starting test of 103 to 93 successfully tested uart 103 93 starting test of 104 to 94 successfully tested uart 104 94 starting test of 105 to 95 successfully tested uart 105 95 starting test of 106 to 96 successfully tested uart 106 96 starting test of 107 to 97 successfully tested uart 107 97 starting test of 108 to 98 successfully tested uart 108 98 starting test of 109 to 99 successfully tested uart 109 99 untested [] bad (one-way) links: {(72, 73)} tested 359 uarts writing configuration tile-id-203-pacman-tile-3-hydra-network.json, including 100 chips 30 30 19 21 100