TILE 1 VDDA: 1876 IDDA: 150.0 VDDD: 1656 IDDD: 520.0 TILE 2 VDDA: 1876 IDDA: 145.0 VDDD: 1672 IDDD: 510.0 TILE 3 VDDA: 1868 IDDA: 155.0 VDDD: 1664 IDDD: 510.0 TILE 4 VDDA: 1872 IDDA: 120.0 VDDD: 1672 IDDD: 525.0 TILE 5 VDDA: 1864 IDDA: 95.0 VDDD: 1664 IDDD: 465.0 TILE 6 VDDA: 1860 IDDA: 105.0 VDDD: 1664 IDDD: 700.0 TILE 7 VDDA: 1868 IDDA: 100.0 VDDD: 1664 IDDD: 445.0 TILE 8 VDDA: 1864 IDDA: 105.0 VDDD: 1672 IDDD: 435.0 verified root chip 11 verified root chip 41 verified root chip 71 unable to verify root chip 101 good root chips: [11, 41, 71] [11, 41, 71] TILE 1 VDDA: 1876 IDDA: 140.0 VDDD: 1660 IDDD: 510.0 TILE 2 VDDA: 1872 IDDA: 130.0 VDDD: 1668 IDDD: 530.0 TILE 3 VDDA: 1868 IDDA: 130.0 VDDD: 1664 IDDD: 525.0 TILE 4 VDDA: 1876 IDDA: 120.0 VDDD: 1672 IDDD: 515.0 TILE 5 VDDA: 1860 IDDA: 95.0 VDDD: 1664 IDDD: 470.0 TILE 6 VDDA: 1860 IDDA: 90.0 VDDD: 1668 IDDD: 690.0 TILE 7 VDDA: 1868 IDDA: 90.0 VDDD: 1664 IDDD: 455.0 TILE 8 VDDA: 1868 IDDA: 100.0 VDDD: 1672 IDDD: 430.0 path including 100 chips 1-13-12 True 1-14-42 True 1-15-72 True 1-13-13 True 1-14-43 True 1-15-73 True 1-13-14 True 1-14-44 True 1-15-74 True 1-13-15 True 1-14-45 True 1-15-75 True 1-13-16 True 1-14-46 True 1-15-76 True 1-13-17 True 1-14-47 True 1-15-77 True 1-13-18 True 1-14-48 True 1-15-78 True 1-13-19 True 1-14-49 True 1-15-79 True 1-13-20 True 1-14-50 False 1-15-80 True 1-13-30 True 1-15-90 True 1-13-29 True 1-15-89 True 1-13-28 True 1-15-88 True 1-13-27 True 1-15-87 True 1-13-26 True 1-15-86 True 1-13-25 True 1-15-85 True 1-13-24 True 1-15-84 True 1-13-23 True 1-15-83 True 1-13-22 True 1-15-82 True 1-13-21 True 1-15-81 True 1-13-31 True 1-15-91 True 1-13-32 True 1-15-92 True 1-13-33 True 1-15-93 True 1-13-34 True 1-15-94 True 1-13-35 True 1-15-95 True 1-13-36 True 1-15-96 True 1-13-37 True 1-15-97 True 1-13-38 True 1-15-98 True 1-13-39 True 1-15-99 True 1-13-40 True 1-15-100 True 1-15-110 True 1-15-109 True 1-15-108 True 1-15-107 True 1-15-106 True 1-15-105 True 1-15-104 True 1-15-103 True 1-15-102 True 1-15-101 True TILE 1 VDDA: 1872 IDDA: 140.0 VDDD: 1660 IDDD: 530.0 TILE 2 VDDA: 1872 IDDA: 135.0 VDDD: 1672 IDDD: 515.0 TILE 3 VDDA: 1868 IDDA: 150.0 VDDD: 1664 IDDD: 520.0 TILE 4 VDDA: 1876 IDDA: 135.0 VDDD: 1668 IDDD: 515.0 TILE 5 VDDA: 1860 IDDA: 90.0 VDDD: 1664 IDDD: 450.0 TILE 6 VDDA: 1864 IDDA: 105.0 VDDD: 1668 IDDD: 690.0 TILE 7 VDDA: 1868 IDDA: 90.0 VDDD: 1664 IDDD: 455.0 TILE 8 VDDA: 1864 IDDA: 95.0 VDDD: 1672 IDDD: 425.0 path inlcuding 100 chips 1-13-21 True 1-14-51 True 1-15-81 True 1-13-31 already verified 1-14-61 True 1-15-91 already verified 1-13-32 already verified 1-14-62 True 1-15-101 True 1-13-42 True 1-14-72 True 1-15-102 already verified 1-13-52 True 1-14-82 True 1-15-92 True 1-13-53 True 1-14-83 already verified 1-15-93 already verified 1-13-63 True 1-14-73 True 1-15-103 True 1-13-64 True 1-14-74 already verified 1-15-104 already verified 1-13-54 True 1-14-84 True 1-15-94 True 1-13-44 True 1-14-85 already verified 1-15-95 already verified 1-13-43 already verified 1-14-75 True 1-15-105 True 1-13-33 True 1-14-65 True 1-15-106 already verified 1-13-23 True 1-14-55 True 1-15-96 True 1-13-22 already verified 1-14-45 True 1-15-86 True 1-13-12 True 1-14-35 True 1-15-76 True 1-13-13 already verified 1-14-34 already verified 1-15-66 True 1-13-14 already verified 1-14-24 True 1-15-56 True 1-13-15 already verified 1-14-25 already verified 1-15-46 True 1-13-16 already verified 1-14-26 already verified 1-15-36 True 1-13-17 already verified 1-14-27 already verified 1-15-37 already verified 1-13-18 already verified 1-14-28 already verified 1-15-47 True 1-13-19 already verified 1-14-38 True 1-15-57 True 1-13-29 True 1-14-48 True 1-15-67 True 1-13-39 True 1-14-58 True 1-15-77 True 1-13-49 True 1-14-68 True 1-15-87 True 1-13-59 True 1-14-78 True 1-15-97 True 1-13-69 True 1-14-88 True 1-15-107 True 1-13-79 True 1-14-98 True 1-15-108 already verified 1-13-89 True 1-14-99 already verified 1-15-109 already verified 1-13-90 already verified 1-14-100 already verified 1-15-110 already verified 1-13-80 already verified 1-13-70 True 1-13-60 True 1-13-50 True 1-13-40 True 1-13-30 True 1-13-20 already verified *************************************** ***Starting Test of Individual Chips*** *************************************** starting test of 31 to 41 successfully tested uart 31 41 starting test of 32 to 22 successfully tested uart 32 22 starting test of 52 to 51 successfully tested uart 52 51 starting test of 52 to 62 successfully tested uart 52 62 starting test of 53 to 54 successfully tested uart 53 54 starting test of 53 to 43 successfully tested uart 53 43 starting test of 63 to 62 successfully tested uart 63 62 starting test of 63 to 73 successfully tested uart 63 73 starting test of 64 to 65 successfully tested uart 64 65 starting test of 64 to 74 successfully tested uart 64 74 starting test of 54 to 55 successfully tested uart 54 55 starting test of 44 to 34 successfully tested uart 44 34 starting test of 23 to 13 successfully tested uart 23 13 starting test of 14 to 24 successfully tested uart 14 24 starting test of 15 to 25 successfully tested uart 15 25 starting test of 16 to 26 successfully tested uart 16 26 starting test of 17 to 27 successfully tested uart 17 27 starting test of 18 to 28 successfully tested uart 18 28 starting test of 49 to 50 49 50 2 sided connection broken starting test of 59 to 60 successfully tested uart 59 60 starting test of 59 to 58 successfully tested uart 59 58 starting test of 69 to 70 successfully tested uart 69 70 starting test of 69 to 68 successfully tested uart 69 68 starting test of 89 to 99 successfully tested uart 89 99 starting test of 90 to 100 successfully tested uart 90 100 not testing, 50 49 starting test of 61 to 71 successfully tested uart 61 71 starting test of 82 to 92 successfully tested uart 82 92 starting test of 83 to 93 successfully tested uart 83 93 starting test of 84 to 94 successfully tested uart 84 94 starting test of 85 to 95 successfully tested uart 85 95 starting test of 65 to 66 successfully tested uart 65 66 starting test of 55 to 56 successfully tested uart 55 56 starting test of 35 to 25 successfully tested uart 35 25 starting test of 26 to 36 successfully tested uart 26 36 starting test of 27 to 37 successfully tested uart 27 37 starting test of 58 to 57 successfully tested uart 58 57 starting test of 68 to 67 successfully tested uart 68 67 starting test of 98 to 108 successfully tested uart 98 108 starting test of 99 to 109 successfully tested uart 99 109 starting test of 66 to 67 successfully tested uart 66 67 starting test of 56 to 57 successfully tested uart 56 57 untested [] bad (one-way) links: {(49, 50)} tested 359 uarts writing configuration tile-id-204-pacman-tile-4-hydra-network.json, including 100 chips 38 31 31 100