In This Package:

SimTrigHeaderCnv Class Reference

#include <SimTrigHeaderCnv.h>

Inheritance diagram for SimTrigHeaderCnv:

[legend]Collaboration diagram for SimTrigHeaderCnv:[legend]List of all members.


Public Types
	INVALID_ADDRESS
	INVALID_OBJECT
	NO_MEMORY
	BAD_STORAGE_TYPE
	NO_SOURCE_OBJECT
	ICONVERSIONSVC_LAST_ERROR
	SUCCESS
	NO_INTERFACE
	VERSMISMATCH
	LAST_ERROR
enum	Status
Public Member Functions
	SimTrigHeaderCnv (ISvcLocator *svc)
virtual	~SimTrigHeaderCnv ()
StatusCode	PerToTran (const PerSimTrigHeader &perobj, DayaBay::SimTrigHeader &tranobj)
	Copy data from TObject based class of type TType to DataObject based class of type DOType.
StatusCode	TranToPer (const DayaBay::SimTrigHeader &tranobj, PerSimTrigHeader &perobj)
	Copy data from DataObject based class of type DOType to TObject based class of type TType.
StatusCode	fillRepRefs (IOpaqueAddress addr, DataObject dobj)
StatusCode	fillObjRefs (IOpaqueAddress addr, DataObject dobj)
PerSimTrigCommandHeader *	convert (const DayaBay::SimTrigCommandHeader &trigCH)
PerSimTrigCommandCollection *	convert (const DayaBay::SimTrigCommandCollection &trigCC)
PerSimTrigCommand *	convert (const DayaBay::SimTrigCommand &trigCom)
DayaBay::SimTrigCommandHeader *	convert (const PerSimTrigCommandHeader &PerSimTrigCH)
DayaBay::SimTrigCommandCollection *	convert (const PerSimTrigCommandCollection &PerSimTrigCC)
DayaBay::SimTrigCommand *	convert (const PerSimTrigCommand &PerSimTrigCom)
PerSimTrigHeader &	getPerInputObject ()
PerSimTrigHeader &	getPerOutputObject ()
const RootIOBaseObject *	getBaseInputObject ()
const RootIOBaseObject *	getBaseOutputObject ()
virtual StatusCode	TranObjectToPerObject (DataObject &dat, const RootOutputAddress &)
virtual StatusCode	PerObjectToTranObject (DataObject *&dat)
virtual RootInputStream *	makeInputStream (const RootInputAddress &ria)
virtual RootOutputStream *	makeOutputStream (const RootOutputAddress &ria)
virtual long	repSvcType () const
virtual StatusCode	initialize ()
virtual StatusCode	finalize ()
virtual StatusCode	createObj (IOpaqueAddress addr, DataObject &dat)
virtual StatusCode	createRep (DataObject pObject, IOpaqueAddress &refpAddress)
int	commit (const RootOutputAddress &roa)
RootIOBaseCnv *	otherConverter (int clID)
virtual StatusCode	queryInterface (const InterfaceID &riid, void **ppvInterface)
virtual unsigned long	addRef ()
virtual unsigned long	release ()
virtual StatusCode	setDataProvider (IDataProviderSvc *svc)
virtual IDataProviderSvc *	dataProvider () const
virtual StatusCode	setConversionSvc (IConversionSvc *svc)
virtual IConversionSvc *	conversionSvc () const
virtual StatusCode	setAddressCreator (IAddressCreator *creator)
virtual IAddressCreator *	addressCreator () const
virtual const CLID &	objType () const
virtual long	i_repSvcType () const
virtual StatusCode	updateObj (IOpaqueAddress pAddress, DataObject refpObject)
virtual StatusCode	updateObjRefs (IOpaqueAddress pAddress, DataObject pObject)
virtual StatusCode	updateRep (IOpaqueAddress pAddress, DataObject pObject)
virtual StatusCode	updateRepRefs (IOpaqueAddress pAddress, DataObject pObject)
StatusCode	service (const std::string &name, T *&psvc, bool createIf=false) const
StatusCode	service (const std::string &type, const std::string &name, T *&psvc) const
Static Public Member Functions
static const CLID &	classID ()
static unsigned char	storageType ()
static const InterfaceID &	interfaceID ()
static const InterfaceID &	interfaceID ()
Public Attributes
	INVALID_ADDRESS
	INVALID_OBJECT
	NO_MEMORY
	BAD_STORAGE_TYPE
	NO_SOURCE_OBJECT
	ICONVERSIONSVC_LAST_ERROR
Protected Member Functions
ISvcLocator *	serviceLocator () const
IMessageSvc *	msgSvc () const
IMessageSvc *	messageService () const
IDataManagerSvc *	dataManager () const
Protected Attributes
std::string	m_perclassName
PerSimTrigHeader *	m_perInObj
PerSimTrigHeader *	m_perOutObj
IRootIOSvc *	m_rioSvc
IConversionSvc *	m_cnvSvc
RootInputStream *	m_ris

Detailed Description

Definition at line 25 of file SimTrigHeaderCnv.h.

Constructor & Destructor Documentation

SimTrigHeaderCnv::SimTrigHeaderCnv ( ISvcLocator * svc )

Definition at line 16 of file SimTrigHeaderCnv.cc.

00017     : RootIOTypedCnv<PerSimTrigHeader,SimTrigHeader>("PerSimTrigHeader",
00018                                                 classID(),svc)
00019 {
00020 }

SimTrigHeaderCnv::~SimTrigHeaderCnv ( ) [virtual]

Definition at line 22 of file SimTrigHeaderCnv.cc.

00023 {
00024 }

Member Function Documentation

static const CLID& SimTrigHeaderCnv::classID ( ) [inline, static]

Definition at line 29 of file SimTrigHeaderCnv.h.

00029                                {
00030     return DayaBay::CLID_SimTrigHeader;
00031   }

StatusCode SimTrigHeaderCnv::PerToTran	(	const PerSimTrigHeader &	perobj,
		DayaBay::SimTrigHeader &	tranobj
	)			`[virtual]`

Copy data from TObject based class of type TType to DataObject based class of type DOType.

Implements RootIOTypedCnv< PerSimTrigHeader, DayaBay::SimTrigHeader >.

Definition at line 26 of file SimTrigHeaderCnv.cc.

00028 {
00029   MsgStream log(msgSvc(), "SimTrigHeaderCnv::PerToTran");
00030 
00031   StatusCode sc = HeaderObjectCnv::toTran(perobj,tranobj);
00032   if (sc.isFailure()) return sc;
00033   DayaBay::SimTrigCommandHeader *tch = convert( *(perobj.commandHeader) );
00034   tch->setHeader(&tranobj);
00035   tranobj.setCommandHeader( tch );
00036   
00037   return StatusCode::SUCCESS;
00038 }

StatusCode SimTrigHeaderCnv::TranToPer	(	const DayaBay::SimTrigHeader &	tranobj,
		PerSimTrigHeader &	perobj
	)			`[virtual]`

Copy data from DataObject based class of type DOType to TObject based class of type TType.

Implements RootIOTypedCnv< PerSimTrigHeader, DayaBay::SimTrigHeader >.

Definition at line 40 of file SimTrigHeaderCnv.cc.

00042 { 
00043   MsgStream log(msgSvc(), "SimTrigHeaderCnv::TranToPer");
00044 
00045   StatusCode sc = HeaderObjectCnv::toPer(tranobj,perobj);
00046   if (sc.isFailure()) return sc;
00047 
00048   delete perobj.commandHeader;
00049   
00050   if( tranobj.commandHeader() != 0 ) {
00051     perobj.commandHeader = convert( *(tranobj.commandHeader()) );
00052   }
00053   return StatusCode::SUCCESS;
00054 }

StatusCode SimTrigHeaderCnv::fillRepRefs	(	IOpaqueAddress *	addr,
		DataObject *	dobj
	)			`[virtual]`

Reimplemented from RootIOTypedCnv< PerSimTrigHeader, DayaBay::SimTrigHeader >.

Definition at line 56 of file SimTrigHeaderCnv.cc.

00057 {
00058     MsgStream log(msgSvc(), "SimTrigHeaderCnv::fillRepRefs");
00059     SimTrigHeader* th = dynamic_cast<SimTrigHeader*>(dobj);
00060 
00061     log << MSG::DEBUG
00062         << "Saving links to " << th->inputHeaders().size() 
00063         << " input headers" << endreq;
00064 
00065     StatusCode sc = HeaderObjectCnv::fillPer(m_rioSvc,*th,*m_perOutObj);
00066     if (sc.isFailure()) {
00067         log << MSG::ERROR << "Failed to fill HeaderObject part" << endreq;
00068         return sc;
00069     }
00070 
00071     // ... fill SimTrigHeader part...
00072     return sc;
00073 }

StatusCode SimTrigHeaderCnv::fillObjRefs	(	IOpaqueAddress *	addr,
		DataObject *	dobj
	)			`[virtual]`

Reimplemented from RootIOTypedCnv< PerSimTrigHeader, DayaBay::SimTrigHeader >.

Definition at line 75 of file SimTrigHeaderCnv.cc.

00076 {
00077     MsgStream log(msgSvc(), "SimTrigHeaderCnv::fillObjRefs");
00078     HeaderObject* hobj = dynamic_cast<HeaderObject*>(dobj);
00079     StatusCode sc = HeaderObjectCnv::fillTran(m_rioSvc,*m_perInObj,*hobj);
00080     if (sc.isFailure()) {
00081         log << MSG::ERROR << "Failed to fill HeaderObject part" << endreq;
00082         return sc;
00083     }
00084 
00085     log << MSG::DEBUG
00086         << "Restored links to " << hobj->inputHeaders().size() 
00087         << " input headers" << endreq;
00088 
00089     // ... fill SimTrigHeader part...
00090     return sc;
00091 }

PerSimTrigCommandHeader * SimTrigHeaderCnv::convert ( const DayaBay::SimTrigCommandHeader & trigCH )

Definition at line 95 of file SimTrigHeaderCnv.cc.

00096 { 
00097   MsgStream log(msgSvc(), "SimTrigHeaderCnv::convet Header");
00098   PerSimTrigCommandHeader::PerComVector outCollVec;
00099   SimTrigCommandHeader::detCollMap inCollVec;
00100   inCollVec = trigCH.collections();
00101   SimTrigCommandHeader::detCollMap::iterator it;
00102   log << MSG::DEBUG  <<"** Converting" 
00103             << inCollVec.size()
00104             << " SimTrigCommandCollections."
00105             << endreq;
00106   for(it = inCollVec.begin(); it != inCollVec.end(); ++it){
00107     outCollVec.push_back( convert( *(it->second) ) );
00108   }
00109   return new PerSimTrigCommandHeader(outCollVec);
00110 }

PerSimTrigCommandCollection * SimTrigHeaderCnv::convert ( const DayaBay::SimTrigCommandCollection & trigCC )

Definition at line 112 of file SimTrigHeaderCnv.cc.

00113 {
00114   PerSimTrigCommandCollection::CommandVectors out_commands;
00115   SimTrigCommandCollection::CommandContainer in_commands = trigCC.commands();
00116   SimTrigCommandCollection::CommandContainer::iterator it;
00117   for(it = in_commands.begin(); it != in_commands.end(); ++it){
00118     out_commands.push_back(convert(**it));
00119   }
00120   short int det = (trigCC.detector()).siteDetPackedData();
00121   return new PerSimTrigCommandCollection(det,out_commands);
00122 }

PerSimTrigCommand * SimTrigHeaderCnv::convert ( const DayaBay::SimTrigCommand & trigCom )

Definition at line 124 of file SimTrigHeaderCnv.cc.

00124                                                                                 {
00125   const int cc = trigCom.clockCycle();
00126   const int type = trigCom.type();
00127   short int det = (trigCom.detector()).siteDetPackedData();
00128   const int nh  = trigCom.nhit();
00129   const int esA = trigCom.esumAdc();
00130   const int esC = trigCom.esumComp();
00131   return new PerSimTrigCommand(cc,type,det,nh,esA,esC);
00132 }

DayaBay::SimTrigCommandHeader * SimTrigHeaderCnv::convert ( const PerSimTrigCommandHeader & PerSimTrigCH )

Definition at line 134 of file SimTrigHeaderCnv.cc.

00134                                                                                                  {
00135   // set header pointer after return
00136   SimTrigCommandHeader *out_header = new SimTrigCommandHeader();
00137   
00138   PerSimTrigCommandHeader::PerComVector in_collection = PerSimTrigCH.commandCollections;
00139   PerSimTrigCommandHeader::PerComVector::iterator it;
00140   SimTrigCommandHeader::detCollMap out_collection;
00141   
00142   for(it=in_collection.begin();it!=in_collection.end();++it){
00143     SimTrigCommandCollection *out_cc = convert(**it);
00144     out_header->addCollection(out_cc);
00145     //out_cc->setHeader(out_header);
00146     //out_collection[out_cc->detector()]=out_cc;
00147   }
00148   return out_header;
00149 }

DayaBay::SimTrigCommandCollection * SimTrigHeaderCnv::convert ( const PerSimTrigCommandCollection & PerSimTrigCC )

Definition at line 151 of file SimTrigHeaderCnv.cc.

00151                                                                                                          {
00152   Detector det(PerSimTrigCC.detector);
00153   SimTrigCommandCollection::CommandContainer out_commands;
00154   PerSimTrigCommandCollection::CommandVectors in_commands = PerSimTrigCC.commands;
00155   PerSimTrigCommandCollection::CommandVectors::iterator it;
00156 
00157   for(it = in_commands.begin(); it != in_commands.end(); ++it)
00158   {
00159     out_commands.push_back( convert(**it) );
00160   }
00161 
00162   return new SimTrigCommandCollection(det,out_commands);
00163 }

DayaBay::SimTrigCommand * SimTrigHeaderCnv::convert ( const PerSimTrigCommand & PerSimTrigCom )

Definition at line 165 of file SimTrigHeaderCnv.cc.

00165                                                                                       {
00166   MsgStream log(msgSvc(), "SimTrigHeaderCnv::convet PerSimTrigCommand");
00167   Detector det(PerSimTrigCom.detector);
00168   Trigger::TriggerType_t ttype=(Trigger::TriggerType_t)PerSimTrigCom.type;
00169   SimTrigCommand *out_command = new SimTrigCommand(det,ttype,PerSimTrigCom.clockCycle,PerSimTrigCom.nhit,PerSimTrigCom.esumAdc,PerSimTrigCom.esumComp);
00170   log << MSG::VERBOSE  <<"** Created" 
00171       << *out_command << endreq;
00172   return out_command;
00173 }

PerSimTrigHeader & RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::getPerInputObject ( ) [inherited]

PerSimTrigHeader & RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::getPerOutputObject ( ) [inherited]

const RootIOBaseObject * RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::getBaseInputObject ( ) [virtual, inherited]

Implements RootIOBaseCnv.

const RootIOBaseObject * RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::getBaseOutputObject ( ) [virtual, inherited]

Implements RootIOBaseCnv.

virtual StatusCode RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::TranObjectToPerObject	(	DataObject &	dat,
		const RootOutputAddress &
	)			`[virtual, inherited]`

Implements RootIOBaseCnv.

virtual StatusCode RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::PerObjectToTranObject ( DataObject *& dat ) [virtual, inherited]

Implements RootIOBaseCnv.

virtual RootInputStream * RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::makeInputStream ( const RootInputAddress & ria ) [virtual, inherited]

Implements RootIOBaseCnv.

virtual RootOutputStream * RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::makeOutputStream ( const RootOutputAddress & ria ) [virtual, inherited]

Implements RootIOBaseCnv.

virtual long RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::repSvcType ( ) const [virtual, inherited]

Reimplemented from RootIOBaseCnv.

virtual StatusCode RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::initialize ( ) [virtual, inherited]

Reimplemented from RootIOBaseCnv.

virtual StatusCode RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::finalize ( ) [virtual, inherited]

Reimplemented from RootIOBaseCnv.

virtual StatusCode RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::createObj	(	IOpaqueAddress *	addr,
		DataObject *&	dat
	)			`[virtual, inherited]`

Reimplemented from RootIOBaseCnv.

virtual StatusCode RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::createRep	(	DataObject *	pObject,
		IOpaqueAddress *&	refpAddress
	)			`[virtual, inherited]`

Reimplemented from RootIOBaseCnv.

int RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::commit ( const RootOutputAddress & roa ) [inherited]

Reimplemented from RootIOBaseCnv.

RootIOBaseCnv * RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::otherConverter ( int clID ) [inherited]

Reimplemented from RootIOBaseCnv.

virtual StatusCode RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::queryInterface	(	const InterfaceID &	riid,
		void **	ppvInterface
	)			`[virtual, inherited]`

Reimplemented from RootIOBaseCnv.

virtual unsigned long RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::addRef ( ) [virtual, inherited]

Reimplemented from RootIOBaseCnv.

virtual unsigned long RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::release ( ) [virtual, inherited]

Reimplemented from RootIOBaseCnv.

virtual StatusCode RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::setDataProvider ( IDataProviderSvc * svc ) [virtual, inherited]

Reimplemented from RootIOBaseCnv.

virtual IDataProviderSvc * RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::dataProvider ( ) const [virtual, inherited]

Reimplemented from RootIOBaseCnv.

virtual StatusCode RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::setConversionSvc ( IConversionSvc * svc ) [virtual, inherited]

Reimplemented from RootIOBaseCnv.

virtual IConversionSvc * RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::conversionSvc ( ) const [virtual, inherited]

Reimplemented from RootIOBaseCnv.

virtual StatusCode RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::setAddressCreator ( IAddressCreator * creator ) [virtual, inherited]

Reimplemented from RootIOBaseCnv.

virtual IAddressCreator * RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::addressCreator ( ) const [virtual, inherited]

Reimplemented from RootIOBaseCnv.

virtual const CLID & RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::objType ( ) const [virtual, inherited]

Reimplemented from RootIOBaseCnv.

virtual long RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::i_repSvcType ( ) const [virtual, inherited]

Reimplemented from RootIOBaseCnv.

virtual StatusCode RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::updateObj	(	IOpaqueAddress *	pAddress,
		DataObject *	refpObject
	)			`[virtual, inherited]`

Reimplemented from RootIOBaseCnv.

virtual StatusCode RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::updateObjRefs	(	IOpaqueAddress *	pAddress,
		DataObject *	pObject
	)			`[virtual, inherited]`

Reimplemented from RootIOBaseCnv.

virtual StatusCode RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::updateRep	(	IOpaqueAddress *	pAddress,
		DataObject *	pObject
	)			`[virtual, inherited]`

Reimplemented from RootIOBaseCnv.

virtual StatusCode RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::updateRepRefs	(	IOpaqueAddress *	pAddress,
		DataObject *	pObject
	)			`[virtual, inherited]`

Reimplemented from RootIOBaseCnv.

StatusCode RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::service	(	const std::string &	name,
		T *&	psvc,
		bool	createIf = `false`
	)			const `[inherited]`

Reimplemented from RootIOBaseCnv.

StatusCode RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::service	(	const std::string &	type,
		const std::string &	name,
		T *&	psvc
	)			const `[inherited]`

Reimplemented from RootIOBaseCnv.

static unsigned char RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::storageType ( ) [static, inherited]

Reimplemented from RootIOBaseCnv.

static const InterfaceID & RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::interfaceID ( ) [static, inherited]

Reimplemented from RootIOBaseCnv.

static const InterfaceID & RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::interfaceID ( ) [static, inherited]

Reimplemented from RootIOBaseCnv.

ISvcLocator * RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::serviceLocator ( ) const [protected, inherited]

Reimplemented from RootIOBaseCnv.

IMessageSvc * RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::msgSvc ( ) const [protected, inherited]

Reimplemented from RootIOBaseCnv.

IMessageSvc * RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::messageService ( ) const [protected, inherited]

Reimplemented from RootIOBaseCnv.

IDataManagerSvc * RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::dataManager ( ) const [protected, inherited]

Reimplemented from RootIOBaseCnv.

Member Data Documentation

RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::INVALID_ADDRESS [inherited]

Reimplemented from RootIOBaseCnv.

RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::INVALID_OBJECT [inherited]

Reimplemented from RootIOBaseCnv.

RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::NO_MEMORY [inherited]

Reimplemented from RootIOBaseCnv.

RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::BAD_STORAGE_TYPE [inherited]

Reimplemented from RootIOBaseCnv.

RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::NO_SOURCE_OBJECT [inherited]

Reimplemented from RootIOBaseCnv.

RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::ICONVERSIONSVC_LAST_ERROR [inherited]

Reimplemented from RootIOBaseCnv.

std::string RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::m_perclassName [protected, inherited]

PerSimTrigHeader * RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::m_perInObj [protected, inherited]

PerSimTrigHeader * RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::m_perOutObj [protected, inherited]

IRootIOSvc * RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::m_rioSvc [protected, inherited]

Reimplemented from RootIOBaseCnv.

IConversionSvc * RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::m_cnvSvc [protected, inherited]

Reimplemented from RootIOBaseCnv.

RootInputStream * RootIOTypedCnv< PerSimTrigHeader , DayaBay::SimTrigHeader >::m_ris [protected, inherited]

Reimplemented from RootIOBaseCnv.

The documentation for this class was generated from the following files:

/home/dayabay/installs/trunk_2011_04_11_opt/NuWa-trunk/dybgaudi/RootIO/PerSimTrigEvent/src/components/SimTrigHeaderCnv.h
/home/dayabay/installs/trunk_2011_04_11_opt/NuWa-trunk/dybgaudi/RootIO/PerSimTrigEvent/src/components/SimTrigHeaderCnv.cc

Generated on Mon Apr 11 20:31:14 2011 for PerSimTrigEvent by 1.4.7

In This Package:

SimTrigHeaderCnv Class Reference

Public Types

Public Member Functions

Static Public Member Functions

Public Attributes

Protected Member Functions

Protected Attributes

Detailed Description

Constructor & Destructor Documentation

Member Function Documentation

Member Data Documentation