SuperLU Distributed 8.2.1
Distributed memory sparse direct solver
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Solves a system of linear equations A*X=B. More...
Functions | |
void | pdgssvx (superlu_dist_options_t *options, SuperMatrix *A, dScalePermstruct_t *ScalePermstruct, double B[], int ldb, int nrhs, gridinfo_t *grid, dLUstruct_t *LUstruct, dSOLVEstruct_t *SOLVEstruct, double *berr, SuperLUStat_t *stat, int *info) |
Solves a system of linear equations A*X=B.
Copyright (c) 2003, The Regents of the University of California, through Lawrence Berkeley National Laboratory (subject to receipt of any required approvals from U.S. Dept. of Energy)
All rights reserved.
The source code is distributed under BSD license, see the file License.txt at the top-level directory.
-- Distributed SuperLU routine (version 6.0) -- Lawrence Berkeley National Lab, Univ. of California Berkeley. November 1, 2007 October 22, 2012 October 1, 2014 April 5, 2015 December 31, 2015 version 4.3 December 31, 2016 version 5.1.3 April 10, 2018 version 5.3 September 18, 2018 version 6.0
void pdgssvx | ( | superlu_dist_options_t * | options, |
SuperMatrix * | A, | ||
dScalePermstruct_t * | ScalePermstruct, | ||
double | B[], | ||
int | ldb, | ||
int | nrhs, | ||
gridinfo_t * | grid, | ||
dLUstruct_t * | LUstruct, | ||
dSOLVEstruct_t * | SOLVEstruct, | ||
double * | berr, | ||
SuperLUStat_t * | stat, | ||
int * | info | ||
) |
Purpose ======= PDGSSVX solves a system of linear equations A*X=B, by using Gaussian elimination with "static pivoting" to compute the LU factorization of A. Static pivoting is a technique that combines the numerical stability of partial pivoting with the scalability of Cholesky (no pivoting), to run accurately and efficiently on large numbers of processors. See our paper at http://www.nersc.gov/~xiaoye/SuperLU/ for a detailed description of the parallel algorithms. The input matrices A and B are distributed by block rows. Here is a graphical illustration (0-based indexing): A B 0 --------------- ------ | | | | | | P0 | | | | | | --------------- ------
grid, a structure describing the 2D processor mesh